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HIP4020
June 1997
Half Amp Full Bridge Power Driver for Small 3V, 5V and 12V DC Motors
Description
In the Functional Block Diagram of the HIP4020, the four switches and a load are arranged in an H-Configuration so that the drive voltage from terminals OUTA and OUTB can be cross-switched to change the direction of current flow in the load. This is commonly known as 4-quadrant load control. As shown in the Block Diagram, switches Q1 and Q4 are conducting or in an ON state when current flows from VDD through Q1 to the load, and then through Q4 to terminal VSSB; where load terminal OUTA is at a positive potential with respect to OUTB. Switches Q1 and Q4 are operated synchronously by the control logic. The control logic switches Q3 and Q2 to an open or OFF state when Q1 and Q4 are switched ON. To reverse the current flow in the load, the switch states are reversed where Q1 and Q4 are OFF while Q2 and Q3 are ON. Consequently, current then flows from VDD through Q3, through the load, and through Q2 to terminal VSSA, and load terminal OUTB is then at a positive potential with respect to OUTA. Terminals ENA and ENB are ENABLE Inputs for the Logic A and B Input Controls. The ILF output is an Over-Current Limit Fault Flag Output and indicates a fault condition for either Output A or B or both. The VDD and VSS are the Power Supply reference terminals for the A and B Control Logic Inputs and ILF Output. While the VDD positive power supply terminal is internally connected to each bridge driver, the VSSA and VSSB Power Supply terminals are separate and independent from VSS and may be more negative than the VSS ground reference terminal. The use of level shifters in the gate drive circuitry to the NMOS (low-side) output stages allows controlled level shifting of the output drive relative to ground.
Features
* Two Independent Controlled Complementary MOS Power Output Half H-Drivers (Full-Bridge) for Nominal 3V to 12V Power Supply Operation * Split Voltage Power Supply Option for Output Drivers * Load Switching Capabilities to 0.5A * Single Supply Range +2.5V to +15V * Low Standby Current * CMOS/TTL Compatible Input Logic * Over-Temperature Shutdown Protection * Over-Current Limit Protection * Over-Current Fault Flag Output * Direction, Braking and PWM Control
Applications
* DC Motor Driver * Relay and Solenoid Drivers * Stepper Motor Controller * Air Core Gauge Instrument Driver * Speedometer Displays * Tachometer Displays * Remote Power Switch * Battery Operated Switch Circuits * Logic and Microcontroller Operated Switch
Ordering Information
PART NUMBER HIP4020IB TEMP. RANGE (oC) -40 to 85 PACKAGE 20 Ld SOIC PKG. NO. M20.3
Pinout
HIP4020 SOIC TOP VIEW
NC ILF B2 ENB B1 VSS ENA A1 A2 1 2 3 4 5 6 7 8 9 20 NC
Block Diagram
VDD
OVER TEMP. AND CURRENT LIMIT, LEVEL SHIFT, DRIVE CONTROL
ISENSE
ISENSE Q3
B1 B2 ENB A1 A2 ENA ILF
18 NC 17 OUTB 16 VSSB 15 VSSA 14 OUTA 13 NC 12 VDD 11 NC
CONTROL CONTROL LOGIC A LOGIC B
19 VDD
Q1
OUTB LOAD
TSENSE Q2 Q4 ISENSE ISENSE
OUTA
NC 10
VSS
VSSA
VSSB
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
3976.1
1
HIP4020
Absolute Maximum Ratings
Supply Voltage; VDD to VSS or VSSA or VSSB . . . . . . . . . . . . . . +15V Neg. Output Supply Voltage, (VSSA, VSSB). . . . . . . . . . . . . (Note 1) DC Logic Input Voltage (Each Input) . . . (VSS -0.5V) to (VDD +0.5V) DC Logic Input Current (Each Input) . . . . . . . . . . . . . . . . . . . . .15mA ILF Fault Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA Output Load Current, (Self Limiting, See Elec. Spec.). . . . . IO(LIMIT)
Thermal Information
Thermal Resistance (Typical, Note 1) JA Plastic SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . 105oC/W Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only)
Operating Conditions TA = 25oC
Typical Operating Supply Voltage Range, VDD . . . . . . . . +3 to +12V Low Voltage Logic Retention, Min. VDD . . . . . . . . . . . . . . . . . . . +2V Idle Supply Current; No Load, VDD = +5V . . . . . . . . . . . . . . . 0.8mA Typical P+N Channel rDS(ON) , VDD = +5V, 0.5A Load . . . . . . . . . 2
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Input Leakage Current Low Level Input Voltage High Level Input Voltage ILF Output Low, Sink Current ILF Output High, Source Current Input Capacitance
TA = 25oC, VDD = +5V, VSSA = VSSB = VSS = 0V, Unless Otherwise Specified SYMBOL ILEAK VIL VIH IOH IOL CIN rDS(ON) rDS(ON) rDS(ON) rDS(ON) IO(LIMIT) -IO(LIMIT) IDD VOH VOL VOH VOL IO(LIMIT) -IO(LIMIT) IO(LIMIT) -IO(LIMIT) TSD ISOURCE = 450mA ISINK = 450mA VDD = +3V, ISOURCE = 250mA VDD = +3V, ISINK = 250mA VDD = +12V VDD = +12V VDD = +3V VDD = +3V VDD = +3V, ISOURCE = 250mA VDD = +3V, ISINK = 250mA VDD = +12V, ISOURCE = 400mA VDD = +12V, ISINK = 400mA VDD = +6V, VSS = 0V, VSSA = VSSB = -6V VDD = +6V, VSS = 0V, VSSA = VSSB = -6V VOUT = 0.4V, VDD = +12V VOUT = 11.6V, VDD = +12V TEST CONDITIONS VDD = +15V MIN VSS 2 15 480 480 4.2 2.415 480 480 480 480 TYP 2 1.6 1 0.6 0.5 625 800 0.8 4.5 0.4 2.6 0.25 625 800 625 800 145 MAX 25 0.8 VDD -15 2.1 1.5 1.2 1.1 1500 1500 1.5 0.6 0.375 1500 1500 1500 1500 UNITS nA V V mA mA pF mA mA mA V V V V mA mA mA mA
oC
P-Channel rDS(ON), Low Supply Voltage N-Channel rDS(ON), Low Supply Voltage P-Channel rDS(ON), High Supply Voltage N-Channel rDS(ON), High Supply Voltage OUTA, OUTB Source Current Limiting OUTA, OUTB Sink Current Limiting Idle Supply Current; No Load OUTA, OUTB Voltage High OUTA, OUTB Voltage Low OUTA, OUTB Voltage High OUTA, OUTB Voltage Low OUTA, OUTB Source Current Limiting OUTA, OUTB Sink Current Limiting OUTA, OUTB Source Current Limiting OUTA, OUTB Sink Current Limiting Thermal Shutdown
2
HIP4020
Electrical Specifications
PARAMETER Response Time: VEN to VOUT Turn-On: Prop Delay Rise Time Turn-Off: Prop Delay Fall Time NOTES: 1. VSS is the required common ground reference for the logic input switching. The load currents may be switched positive and negative in reference to the VSS common ground by using a split supply for VDD (positive) to VSSA and VSSB (negative). For an uneven split in the supply voltage, the Maximum Negative Output Supply Voltage for VSSA and VSSB is limited by the Maximum VDD to VSSA or VSSB ratings. Since the VDD pins are internally tied together, the voltage on each VDD pins must be equal and common. 2. Refer to the Truth Table and the VEN to VOUT Switching Waveforms. Current, IO refers to IOUTA or IOUTB as the Output Load current. Note that ENA controls OUTA and ENB controls OUTB. Each Half H-Switch has independent control from the respective A1, A2, ENA or B1, B2, ENB inputs. Refer to the Terminal Information Table for external pin connections to establish mode control switching. Figure 1 shows a typical application circuit used to control a DC Motor. tPLH tr tPHL tf TA = 25oC, VDD = +5V, VSSA = VSSB = VSS = 0V, Unless Otherwise Specified (Continued) SYMBOL TEST CONDITIONS IO = 0.5A (Note 2) 2.5 4 0.1 0.1 s s s s MIN TYP MAX UNITS
Pin Descriptions
PIN NUMBER 12, 19 SYMBOL VDD DESCRIPTION Positive Power Supply pins; internally common and externally connect to the same Positive Supply (V+). Negative Power Supply pin; Negative or Ground return for Switch Driver A; externally connect to the Supply (V-). Negative Power Supply pin; Negative or Ground return for Switch Driver B; externally connect to the Supply (V-). Common Ground pin for the Input Logic Control circuits. May be used as a common ground with VSSA and VSSB. Input pins used to control the direction of output load current to/from OUTA and OUTB, respectively. When connected, A1 and B1 can be controlled from the same logic signal to change the directional rotation of a motor. Input pins used to force a low state on OUTA and OUTB, respectively. When connected, A2 and B2 can be controlled from the same logic signal to activate Dynamic Braking of a motor. Input pins used to Enable Switch Driver A and Switch Driver B, respectively. When Low, the respective output is in a high impedance (Z) off-state. Since each Switch Driver is independently controlled, OUTA and OUTB may be a separately PWM controlled as Half H-Switch Drivers. Respectively, Switch Driver A and Switch Driver B Output pins. Current Limiting Fault Output Flag pin; when in a high logic state, signifies that Switch Driver A or B or both are in a Current Limiting Fault Mode.
15
VSSA
16
VSSB
6
VSS
8, 5
A1, B1
9, 3
A2, B2
7, 4
ENA, ENB
14, 17 2
OUTA, OUTB ILF
3
HIP4020
V+ VDD
B1 B2 BRAKE ON OFF ENB CONTROL LOGIC B LEVEL SHIFTER AND OC/OT LIMITER Q1 D1
OVER-TEMP LIMIT
Q3 D3
A1 DIRECTION A2 ENA ENABLE CONTROL LOGIC A
Q2
D2
D4
Q4
LEVEL SHIFTER AND OC/OT LIMITER ILF V50% 50%
VSS (LOGIC GROUND)
VSSA
OUTA
OUTB
VSSB
LOAD
FIGURE 1. TYPICAL MOTOR CONTROL APPLICATION CIRCUIT SHOWING DIRECTIONAL AND BRAKING CONTROL
TRUTH TABLE SWITCH DRIVER A INPUTS A1 A2 ENA H L H L X L L H H X H H H H L OUTPUT OUTA OH OL OL OL Z SWITCH DRIVER B INPUTS B1 B2 ENB L H L H X L L H H X H H H H L OUTPUT
VOUT VEN 50% tPLH 10% tr 90%
OUTB OH OL OL OL Z
VOUT VEN
50%
tPHL 10% 90% tf
L = Low logic level; H = High logic level Z = High Impedance (off state) OH = Output High (sourcing current to the output terminal) OL = Output Low (sinking current from the output terminal) X = Don't Care FIGURE 2.
SWITCHING WAVEFORMS
4
HIP4020 Application
The HIP4020 is designed to detect load current feedback from sampling resistors of low value in the source connections of the output drivers to VDD, VSSA and VSSB (See Figure 1). When the sink or source current at OUTA or OUTB exceeds the preset OC (Over-Current) limiting value of 550mA typical, the current is held at the limiting value. If the OT (Over-Temperature) Shutdown Protection limit is exceeded, temperature sensing BiMOS circuits limit the junction temperature to 150oC typical. The circuit of Figure 1 shows the Full H-Switch in a small motordrive application. The left (A) and right (B) H-Switch's are controlled from the A and B inputs via the A and B CONTROL LOGIC to the MOS output transistors Q1, Q2, Q3 and Q4. The circuit is intended to safely start, stop, and control rotational direction for a motor requiring no more than 0.5A of supply current. The stop function includes a Dynamic Braking feature. With the ENABLE Inputs Low, the MOS transistors Q1 and Q3 are OFF; which cuts-off supply current to OUTA and OUTB. With the BRAKE terminal Low and ENABLE Inputs High, either Q1 and Q4 or Q3 and Q2 will be driven into conduction by the DIRECTION Input Control terminal. The MOS output transistor pair chosen for conduction is determined by the logic level applied to the DIRECTION control; resulting in either clockwise (CW) or counter-clockwise (CCW) shaft rotation. When the BRAKE terminal is switched high (while holding the ENABLE input high), the gates of both Q2 and Q4 are driven high. Current flowing through Q2 (from the motor terminal OUTA) at the moment of Dynamic Braking will continue to flow through Q2 to the VSSA and VSSB external connection, and then continue through diode D4 to the motor terminal OUTB. As such, the resistance of the motor winding (and the series-connected path) dissipates the kinetic energy stored in the system. Reversing rotation, current flowing through Q4 (from the motor terminal OUTB), at the moment of Dynamic Braking, would continue to flow through Q4 to the VSSB and VSSA tie, and then continue through diode D2 to the motor terminal OUTA, to dissipate the stored kinetic energy as previously described. Where VDD to VSS are the Power Supply reference terminals for the Control Logic, the lowest practical supply voltage for proper logic control should be no less than 2.0V. The VSSA and VSSB terminals are separate and independent from VSS and may be more negative than the VSS ground reference terminal. However, the maximum supply level from VDD to VSSA or VSSB must not be greater than the Absolute Maximum Supply Voltage rating. Terminals A1, B1, A2, B2, ENA and ENB are internally connected to protection circuits intended to guard the CMOS gate-oxides against damage due to electrostatic discharge. (See Figure 3) Inputs ENA, ENB, A1, B1 A2 and B2 have CD74HCT4000 Logic Interface Protection and Level Converters for TTL or CMOS Input Logic. These inputs are designed to typically provide ESD protection up to 2kV. However, these devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
VDD
INPUT
LEVEL CONV.
FIGURE 3. LOGIC INPUT ESD INTERFACE PROTECTION
VDD
A1 (DIR)
P-DR LIMIT D1 Q1 OUTA Q2 D2
A2 (BRAKE)
OT AND OC PROTECT
ENA (ENABLE)
N-DR LIMIT VSSA VDD
B1 (DIR)
P-DR LIMIT D3 Q3 OUTB Q4 D4
B2 (BRAKE)
OT AND OC PROTECT
ENB (ENABLE)
N-DR LIMIT VSSB
FIGURE 4. EQUIVALENT CONTROL LOGIC A AND B SHOWN DRIVING THE OUTA AND OUTB OUTPUT DRIVERS
5
HIP4020 Typical Performance Curves
800 750 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 0.0 0.1 0.2 0.5 VDD = 12V VDD = 5V VDD = 3V TYPICAL CURRENT LIMITING 1 2 P-CHANNEL DRAIN CURRENT (mA)
0.3
0.4
0.5
0.6
0.7 0.8 0.9 1.0 1.1 1.2 1.3 DRAIN-TO-SOURCE VOLTAGE (V)
1.4
1.5
1.6
1.7
1.8
1.9
2.0
FIGURE 5. TYPICAL CHARACTERISTIC OF THE P-MOSFET OUTPUT DRIVER DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE, TAMBIENT = 25oC
800 750 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 0.0
VDD = 5V 0.5 VDD = 12V 1 VDD = 3V 2 TYPICAL CURRENT LIMITING
N-CHANNEL DRAIN CURRENT (mA)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
DRAIN-TO-SOURCE VOLTAGE (V)
FIGURE 6. TYPICAL CHARACTERISTIC OF THE N-MOSFET OUTPUT DRIVER DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE, TAMBIENT = 25oC
N-CHANNEL 800 750 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 SHORT CIRCUIT CURRENT (mA)
P-CHANNEL
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 VDD SUPPLY VOLTAGE (V)
FIGURE 7. TYPICAL CHARACTERISTIC OF THE P AND N OUTPUT DRIVER SHORT CIRCUIT CURRENT vs SUPPLY VOLTAGE, TAMBIENT = 25oC
6
HIP4020 Typical Performance Curves
0.65 SATURATION VOLTAGE, VDD - VOUT (V) 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 100 200 300 OUTPUT CURRENT, IO (A) 400 500 VSAT(P) VSAT(N) HIP4020 SPLIT 5V COMMON GROUND VSAT vs LOAD CURRENT VDD = +5V VSS = VSSA = VSSB = GND
(Continued)
HIGH LOW
FIGURE 8. TYPICAL CHARACTERISTIC OF SATURATION VOLTAGE vs OUTPUT CURRENT USING A +5V SUPPLY, TAMBIENT = 25oC
0.70 SATURATION VOLTAGE, VDD - VOUT (V) 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 100 200 300 400 OUTPUT CURRENT, IO (A) 500 600 700 LOW VSAT(P) VSAT(N) HIP4020 SPLIT 3V VSAT vs LOAD CURRENT VDD = +3V VSS = GND VSSA = VSSB = -3V
HIGH
FIGURE 9. TYPICAL CHARACTERISTIC OF SATURATION VOLTAGE vs OUTPUT CURRENT USING A 3V SPLIT SUPPLY, OUTPUT REFERENCE EQUAL LOGIC GROUND, TAMBIENT = 25oC
0.70 SATURATION VOLTAGE, VDD - VOUT (V) 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 100 200 300 400 OUTPUT CURRENT, IO (A) 500 600 VSAT(P) VSAT(N) HIGH LOW HIP4020 SPLIT 6V VSAT vs LOAD CURRENT VDD = +6V VSS = GND VSSA = VSSB = -6V
FIGURE 10. TYPICAL CHARACTERISTIC OF SATURATION VOLTAGE vs OUTPUT CURRENT USING A 6V SPLIT SUPPLY, OUTPUT REFERENCE EQUAL LOGIC GROUND, TAMBIENT = 25oC
7
HIP4020 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A A1
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 12.60 7.40 MAX 2.65 0.30 0.51 0.32 13.00 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.4961 0.2914
MAX 0.1043 0.0118 0.0200 0.0125 0.5118 0.2992
B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.394 0.010 0.016 20 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 20 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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